Release in Q2 2025
RISC-V CPU Design: DSP and Scalar VLIW Architecture
IntermediateMaster RISC-V processor design through hands-on projects and practical implementations.
Course Description
• DSP and Vector Unit Design
• Scalar VLIW Architecture
• RV64IMFD Architecture (floating-point)
• Compiler Design for DSP and Scalar VLIW
• Memory Error Detection and Correction
• Includes FPGA And ASIC Implementation Add-on
$ ...
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What's Included
- Lifetime access to course materials
- Project files and source code
- Certificate of completion